library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux4to1 is
	port(s0,s1  : in std_logic;
		a,b,c,d : in std_logic;
		y		: out std_logic);
end;
architecture behave of mux4to1 is

begin
	process(s0,s1,a,b,c,d)
	begin
		if s0 = '0' and s1 ='0' then y<=a;end if;
		if s0 = '0' and s1 ='1' then y<=b;end if;
		if s0 = '1' and s1 ='0' then y<=c;end if;
		if s0 = '1' and s1 ='1' then y<=d;end if;
	end process;
	
end behave;
